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| Back CS8156 12 V, 5.0 V Low Dropout Dual Regulator with ENABLE The CS8156 is a low dropout 12 V/5.0 V dual output linear regulator. The 12 V 5.0% output sources 750 mA and the 5.0 V 2.0% output sources 100 mA. The on board ENABLE function controls the regulator's two outputs. When the ENABLE lead is low, the regulator is placed in SLEEP mode. Both outputs are disabled and the regulator draws only 200 nA of quiescent current. The regulator is protected against overvoltage conditions. Both outputs are protected against short circuit and thermal runaway conditions. The CS8156 is packaged in a 5 lead TO-220 with copper tab. The copper tab can be connected to a heat sink if necessary. 1 http://onsemi.com TO-220 FIVE LEAD T SUFFIX CASE 314D 1 5 TO-220 FIVE LEAD TVA SUFFIX CASE 314K Features * Two Regulated Outputs - 12 V 5.0%; 750 mA - 5.0 V 2.0%; 100 mA * Very Low SLEEP Mode Current Drain 200 nA * Fault Protection - Reverse Battery - +60 V, -50 V Peak Transient Voltage - Short Circuit - Thermal Shutdown * CMOS Compatible ENABLE 1 TO-220 FIVE LEAD THA SUFFIX CASE 314A 5 PIN CONNECTIONS AND MARKING DIAGRAM Tab = GND Pin 1. VIN 2. VOUT1 3. GND 4. ENABLE 5. VOUT2 CS8156 AWLYWW 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device CS8156YT5 CS8156YTVA5 CS8156YTHA5 *Five lead. Package TO-220* STRAIGHT TO-220* VERTICAL TO-220* HORIZONTAL Shipping 50 Units/Rail 50 Units/Rail 50 Units/Rail (c) Semiconductor Components Industries, LLC, 2001 1 January, 2001 - Rev. 7 Publication Order Number: CS8156/D CS8156 VOUT2, 5.0 V VIN Anti-saturation and Current Limit ENABLE - + Pre-Regulator + - VOUT1, 12 V Overvoltage Shutdown Anti-saturation and Current Limit + - Bandgap Reference GND Thermal Shutdown Figure 1. Block Diagram ABSOLUTE MAXIMUM RATINGS* Rating Input Voltage: Internal Power Dissipation Operating Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature Soldering: 1. Load Dump = 46 V 2. 10 second maximum. *The maximum package power dissipation must be observed. Wave Solder (through hole styles only) (Note 2.) Operating Range Peak Transient Voltage (Note 1.) Value -0.5 to 26 60 Internally Limited -40 to +125 -40 to +150 -65 to +150 260 peak Unit V V - C C C C http://onsemi.com 2 CS8156 ELECTRICAL CHARACTERISTICS for VOUT: (VIN = 14.5 V, IOUT1 = 5.0 mA, IOUT2 = 5.0 mA, -40C TJ +150C, -40C TC +125C; unless otherwise specified.) Characteristic Output Stage (VOUT1) Output Voltage, (VOUT1) Dropout Voltage Line Regulation Load Regulation Quiescent Current Quiescent Current (Sleep Mode) Ripple Rejection Current Limit Maximum Line Transient Reverse Polarity Input Voltage, DC Reverse Polarity Input Voltage, Transient Output Noise Voltage Output Impedance Overvoltage Shutdown Standby Output (VOUT2) Output Voltage, (VOUT2) Dropout Voltage Line Regulation Load Regulation Ripple Rejection Current Limit ENABLE Function (ENABLE) Input ENABLE Threshold Input ENABLE Current VOUT1 Off VOUT1 On VENABLE VTHRESHOLD - 2.00 -10 1.25 1.25 0 0.80 - 10 V V A 9.0 V VIN 16 V, 1.0 mA IOUT2 100 mA IOUT2 100 mA 6.0 V VIN 26 V, 1.0 mA IOUT 100 mA 1.0 mA IOUT2 100 mA; 9.0 V VIN 16 V f = 120 Hz; IOUT = 100 mA, VIN = 1.5 VPP at 14.5 VDC - 4.90 - - - 42 100 5.00 - 5.0 5.0 70 200 5.10 0.60 50 50 - - V V mV mV dB mA VOUT1 13 V VOUT1 -0.6 V, 10 Load 1.0% Duty Cycle, t = 100 ms, VOUT -6.0 V, 10 Load 10 Hz - 100 kHz 500 mA DC and 10 mA rms, 100Hz - 13 V VIN 16 V, IOUT1 750 mA IOUT1 = 500 mA IOUT1 = 750 mA 13 V VIN 16 V, 5.0 mA IOUT1 < 100 mA 5.0 mA IOUT1 500 mA IOUT1 500 mA, No Load on Standby IOUT1 750 mA, No Load on Standby ENABLE = Low f = 120 Hz, IOUT = 5.0 mA, VIN = 1.5 VPP at 15.5 VDC - 11.2 - - - - - - 42 0.75 60 -18 -50 - - 28 12.0 0.4 0.6 15 15 45 100 0.2 70 1.20 90 -30 -80 - 0.2 34 12.8 0.6 1.0 80 80 125 250 50 - 2.50 - - - 500 1.0 45 V V V mV mV mA mA A dB A V V V Vrms V Test Conditions Min Typ Max Unit PACKAGE PIN DESCRIPTION PACKAGE LEAD # 5 Lead TO-220 1 2 3 4 5 LEAD SYMBOL VIN VOUT1 GND ENABLE VOUT2 FUNCTION Supply voltage, usually direct from battery. Regulated output 12 V, 750 mA (typ). Ground connection. CMOS compatible input lead; switches outputs on and off. When ENABLE is high VOUT1 and VOUT2 are active. Regulated output 5.0 V, 100 mA (typ). http://onsemi.com 3 CS8156 TYPICAL PERFORMANCE CHARACTERISTICS 2000 1800 Dropout Voltage (mV) 1600 1400 1200 1000 800 600 400 200 0 0 50 100 150 200 13 12 11 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 -1.0 -2.0 RL = 10 Output Voltage (V) -40 -20 0 20 40 60 IOUT (mA) Input Voltage (V) Figure 2. Dropout Voltage vs. IOUT2 Figure 3. VOUT1 vs. Input Voltage 12.15 12.10 12.05 VOUT1 (V) VOUT2 (V) 0 20 40 60 80 100 120 140 160 5.030 5.020 5.010 5.000 4.990 4.980 4.970 12.00 11.95 11.90 11.85 11.80 11.75 -40 -20 -40 -20 0 20 40 60 80 100 120 140 160 Temp (C) Temp (C) Figure 4. VOUT1 vs. Temperature Figure 5. VOUT2 vs. Temperature 100 80 IENABLE (mA) 0 1.0 2.0 3.0 4.0 5.0 5.0 4.0 3.0 2.0 1.0 0 IENABLE (A) 60 40 20 0 0 5.0 10 15 20 25 VENABLE (V) VENABLE (V) Figure 6. ENABLE Current vs. ENABLE Voltage Figure 7. ENABLE Current vs. ENABLE Voltage http://onsemi.com 4 CS8156 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 20 Output Voltage Deviation (mV) Output Voltage Deviation (mV) IOUT1 = 500 mA 10 0 -10 -20 3.0 2.0 1.0 0 0 10 20 30 40 50 60 10 5.0 0 -5.0 -10 IOUT2 = 100 mA Input Voltage Change (V) Input Voltage Chnage (V) 3.0 2.0 1.0 0 0 10 20 30 40 50 60 Time (s) Time (s) Figure 8. Line Transient Response (VOUT1) Figure 9. Line Transient Response (VOUT2) 150 Output Voltage Deviation (mV) Standby Output Voltage Deviation (mV) Standby Load Current (mA) 0 10 20 30 40 50 60 150 100 50 0 -50 -100 -150 20 15 10 5.0 0 0 10 20 30 40 50 60 100 50 0 -50 -100 -150 0.8 0.6 0.4 0.2 0 Time (s) Load Current (A) Time (s) Figure 10. Load Transient Response (VOUT1) 20 18 Quiescent Current (mA) Power Dissipation (W) 16 14 12 10 8.0 6.0 4.0 2.0 0 0 10 20 30 40 50 60 70 80 90 Figure 11. Load Transient Response (VOUT2) 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 No Load on 5.0 V 125C VIN = 14 V 25C Infinite Heat Sink 10C/W Heat Sink -40C No Heat Sink 0 100 200 300 400 500 600 700 800 Ambient Temperature (C) Output Current (mA) Figure 12. Maximum Power Dissipation (TO-220) Figure 13. Quiescent Current vs. Output Current for VOUT2 http://onsemi.com 5 CS8156 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 22 20 Quiescent Current (mA) 18 Line Regulation (mV) 16 14 12 10 8.0 6.0 4.0 2.0 0 0 20 40 60 80 100 120 140 No Load on 5.0 V 3.0 2.0 1.0 0 -1.0 -2.0 -3.0 -4.0 -5.0 -6.0 0 20 40 60 80 100 120 140 VIN = 14 V 25C -40C 125C -40C 25C 125C VIN = 6.0-26 V Output Current (mA) Output Current (mA) Figure 14. Quiescent Current vs. Output Current for VOUT1 0 -2.0 Load Regulation (mV) -4.0 -6.0 -8.0 -10 -12 125C -14 -16 -18 0 20 40 60 80 100 120 140 Figure 15. Line Regulation vs. Output Current for VOUT2 25 20 15 10 5.0 0 -5.0 -10 -15 -20 -25 -30 -35 -40 0 -40C 25C Line Regulation (mV) 125C 25C VIN = 13-26V -40C VIN = 14 V 100 200 300 400 500 600 700 800 Output Current (mA) Output Current (mA) Figure 16. Load Regulation vs. Output Current fo VOUT2 0 -5.0 Load Regulation (mV) -10 -15 -20 -25 -30 VIN = 14 V -35 -40 0 100 200 300 400 500 Figure 17. Line Regulation vs. Output Current for VOUT1 -40C 25C 125C 600 700 800 Output Current (mA) Figure 18. Load Regulation vs. Output Current for VOUT1 http://onsemi.com 6 CS8156 DEFINITION OF TERMS Dropout Voltage - The input-output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100 mV from the nominal value obtained at 14 V input, dropout voltage is dependent upon load current and junction temperature. Input Voltage - The DC voltage applied to the input terminals with respect to ground. Input Output Differential - The voltage difference between the unregulated input voltage and the regulated output voltage for which the regulator will operate. Line Regulation - The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. 60 V VIN 14 V 34 V 3.0 V 26 V 14V Load Regulation - The change in output voltage for a change in load current at constant chip temperature. Long Term Stability - Output voltage stability under accelerated life-test conditions after 1000 hours with maximum rated voltage and junction temperature. Output Noise Voltage - The rms AC voltage at the output, with constant load and no input ripple, measured over a specified frequency range. Quiescent Current - The part of the positive input current that does not contribute to the positive load current, i.e., the regulator ground lead current. Ripple Rejection - The ratio of the peak-to-peak input ripple voltage to the peak-to-peak output ripple voltage. Temperature Stability of VOUT - The percentage change in output voltage for a thermal variation from room temperature to either temperature extreme. ENABLE 2.0 V 0.8 V 12 V 12 V 2.4 V 12 V 0V 5.0 V 5.0 V 2.4 V 0V Turn On Load Dump Low VIN Line Noise, Etc. VOUT1 Short Circuit VOUT1 Thermal Shutdown Turn Off 12 V 12 V 0V VOUT1 VOUT2 0V VOUT2 Short Circuit Figure 19. Typical Circuit Waveform APPLICATION NOTES Stability Considerations The output or compensation capacitor helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the cheapest solution, but, if the circuit operates at low temperatures (-25C to -40C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitors C2 and C3 shown in the test and applications circuit should work for most applications, however it is not necessarily the best solution. To determine acceptable values for C2 and C3 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part for each output. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor C2 will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations http://onsemi.com 7 CS8156 are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found for each output, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitors should be less than 50% of the maximum allowable ESR found in step 3 above. Repeat steps 1 through 7 with C3, the capacitor on the other output. Calculating Power Dissipation in a Dual Output Linear Regulator IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RJA can be calculated: RQJA + 150C * TA PD (2) The value of RJA can be compared with those in the package section of the data sheet. Those packages with RJA's less than the calculated value in equation 2 will keep the die temperature below 150C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IIN VIN IOUT1 VOUT1 Smart Regulator Control Features IOUT2 VOUT2 IQ Figure 20. Dual Output Regulator With Key Performance Parameters Labeled. Heat Sinks A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RJA: RQJA + RQJC ) RQCS ) RQSA (3) The maximum power dissipation for a dual output regulator (Figure 20) is PD(max) + VIN(max) * VOUT1(min) IOUT1(max) ) VIN(max) * VOUT2(min) IOUT2(max) ) VIN(max)IQ (1) where: VIN(max) is the maximum input voltage, VOUT1(min) is the minimum output voltage from VOUT1, VOUT2(min) is the minimum output voltage from VOUT2, IOUT1(max) is the maximum output current, for the application, IOUT2(max) is the maximum output current, for the application, and where: RJC = the junction-to-case thermal resistance, RCS = the case-to-heatsink thermal resistance, and RSA = the heatsink-to-ambient thermal resistance. RJC appears in the package section of the data sheet. Like RJA, it too is a function of package type. RCS and RSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. http://onsemi.com 8 CS8156 C1 * 0.1 F VIN CS8156 ENABLE VOUT2 + VOUT1 + C2** 22 F C3** 22 F GND * C1 is required if the regulator is far from power supply filter. ** C2, C3 required for stability. Figure 21. Test & Application Circuit http://onsemi.com 9 CS8156 PACKAGE DIMENSIONS TO-220 FIVE LEAD T SUFFIX CASE 314D-04 ISSUE E -T- -Q- B C E SEATING PLANE U K 12345 A L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. DIM A B C D E G H J K L Q U INCHES MIN MAX 0.572 0.613 0.390 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.067 BSC 0.087 0.112 0.015 0.025 0.990 1.045 0.320 0.365 0.140 0.153 0.105 0.117 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 4.318 4.572 0.635 0.965 1.219 1.397 1.702 BSC 2.210 2.845 0.381 0.635 25.146 26.543 8.128 9.271 3.556 3.886 2.667 2.972 G D 5 PL J H M 0.356 (0.014) M TQ TO-220 FIVE LEAD TVA SUFFIX CASE 314K-01 ISSUE O -T- C -Q- B E SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.027 0.037 0.045 0.055 0.530 0.545 0.067 BSC 0.014 0.022 0.785 0.800 0.321 0.337 0.063 0.078 0.146 0.156 0.271 0.321 0.146 0.196 0.460 0.475 5 MILLIMETERS MIN MAX 14.22 14.99 9.78 10.54 4.06 4.83 0.69 0.94 1.14 1.40 13.46 13.84 1.70 BSC 0.36 0.56 19.94 20.32 8.15 8.56 1.60 1.98 3.71 3.96 6.88 8.15 3.71 4.98 11.68 12.07 5 W A L 1 2 3 4 5 U F K M J M DIM A B C D E F G J K L M Q R S U W D 0.356 (0.014) M 5 PL TQ G R S http://onsemi.com 10 CS8156 TO-220 FIVE LEAD THA SUFFIX CASE 314A-03 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 0.043 (1.092) MAXIMUM. INCHES MIN MAX 0.572 0.613 0.390 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.570 0.585 0.067 BSC 0.015 0.025 0.730 0.745 0.320 0.365 0.140 0.153 0.210 0.260 0.468 0.505 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 4.318 4.572 0.635 0.965 1.219 1.397 14.478 14.859 1.702 BSC 0.381 0.635 18.542 18.923 8.128 9.271 3.556 3.886 5.334 6.604 11.888 12.827 -T- B -P- OPTIONAL CHAMFER SEATING PLANE C E Q U A L F K G 5X 5X J D 0.014 (0.356) M S TP M DIM A B C D E F G J K L Q S U PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical TO-220 FIVE LEAD 2.0 50 Unit C/W C/W http://onsemi.com 11 CS8156 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (Mon-Fri 2:30pm to 7:00pm CET) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (Mon-Fri 2:00pm to 7:00pm CET) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (Mon-Fri 12:00pm to 5:00pm GMT) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, UK, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 12 CS8156/D |
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